Biography

Jyotika Athavale is a Senior Technical Leader and Functional Safety Architect at Nvidia Corporation. She is a recognized industry expert with in-depth technical knowledge of platform technologies and architectures for Automotive, Transportation and Avionics Safety Critical Systems, also with expertise in radiation effects modeling for soft errors performance. Based in the US, her 24 years of industry career experience in the semiconductor and EDA industry has spanned technical leadership positions as well as people management roles.

Jyotika is a board member of the IEEE Computer Society Board of Governors and a Distinguished Visitor with the IEEE Computer Society. She is also one of the IEEE Computer Society representatives to the IEEE Systems Council. Jyotika is currently leading and influencing international standards activities in the area of functional safety. A frequent conference speaker at international leading conferences, she actively contributes to these IEEE events via papers, invited talks and panel presentations. Jyotika has authored several IEEE publications and is a core team member of the IEEE Computer Society Special Technical Community for Reliable, Safe, Secure and Time Deterministic Intelligent Systems. She is an active mentor to IEEE Student Members in IEEE Region 6 and holds a master’s degree in electrical engineering from Iowa State University.

Intel Corporation

Email: jathavale@nvidia.com

DVP term expires December 2023

Presentations

Functional Safety and Soft Error Rate Modeling for Deep Learning Applications

Compliance to FuSa metrics and SER requirements pose challenges for safety critical systems. This talk will focus on soft error rate modeling for functional safety, with a focus on product vulnerability factors for AI and Deep Learning applications. It will describe different considerations and approaches for derating, based on workloads, and will highlight methodologies to architect and design for transient reliability and safety in the context of artificial intelligence.

Chip-Level Considerations to Enable Dependability for eVTOL and Urban Air Mobility Systems

Weight, energy consumption and performance are critical drivers in future mass-produced eVTOLs (electrically powered Vertical Take-Off and Landing aircraft) worldwide. The quest to rapidly integrate and certify modern COTS compute and communications technology will be a central goal of modern avionics OEMs combining new technologies, like cloud-center-like integration and acceleration like AI, to create new functionality necessary for the Urban Air Mobility (UAM) revolution. The cost savings in COTS, to be fully recognized, will require a new perspective on how functionality is partitioned, how power-efficient and safe/secure performance is facilitated by multicore processors (MCP) and how the HW/SW certification processes can be streamlined to allow the industry to easily absorb the latest innovations.
This presentation will describe some current and future trends that affect air traffic control systems and UAM avionics, including impacts on Air Traffic Control (ATC) and will present how new ATC and UAM avionics architectures, technology enablers in general and how UAM profit from specific technology from different chip vendors.

Technology Challenges for Functional Safety and Real Time Coexistence

This presentation establishes a common ground for the coexistence of functional safety and temporal requirements for safety-critical systems built on complex multiprocessor hardware. Although studied for many years, this problem is rapidly increasing in importance and far from being solved. The talk will include real-world use cases which highlight requirements and design challenges that system integrators face when building such complex software-defined systems, and how they complicate system validation and certification. Armed with that, we discuss potential solutions and how chip vendors can help its customers achieve their product goals.